MC9S12DT256_06 Datasheet, PDF (80/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
6.6 HCS12 Breakpoint (BKP) Block Description
Consult the BKP Block guide for information on HCS12 breakpoint block
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 8 Enhanced Capture Timer (ECT) Block
Description
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module
When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT256.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module.When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 11 Serial Communications Interface (SCI) Block
Description
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