MC9S12DT256_06 Datasheet, PDF (123/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

A.8 External Bus Timing
MC9S12DT256 Device User Guide — V03.07
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing
values shown on table Table A-21. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
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