MC9S12DT256_06 Datasheet, PDF (120/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT²
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12
BIT 6 . . . 1
11
BIT 6 . . . 1
13
3
13
LSB IN
MASTER LSB OUT
PORT DATA
Figure A-7 SPI Master Timing (CPHA=1)
In Table A-19 the timing characteristics for master mode are listed.
Table A-19 SPI Master Mode Timing Characteristics
Num
Characteristic
1 SCK Frequency
1 SCK Period
2 Enable Lead Time
3 Enable Lag Time
4 Clock (SCK) High or Low Time
5 Data Setup Time (Inputs)
6 Data Hold Time (Inputs)
9 Data Valid after SCK Edge
10 Data Valid after SS fall (CPHA=0)
11 Data Hold Time (Outputs)
12 Rise and Fall Time Inputs
13 Rise and Fall Time Outputs
Symbol
f_sck
t_sck
t_lead
t_lag
t_wsck
t_su
t_hi
t_vsck
t_vss
t_ho
t_r
t_rfo
Min
1/2048
2
—
—
—
8
8
—
—
20
—
—
Typ
—
—
1/2
1/2
1/2
—
—
—
—
—
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
120