MC9S12DT256_06 Datasheet, PDF (119/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

A.7 SPI
MC9S12DT256 Device User Guide — V03.07
This section provides electrical parametrics and ratings for the SPI.
In Table A-18 the measurement conditions are listed.
Table A-18 Measurement Conditions
Description
Drive mode
Load capacitance C_LOAD,
on all outputs
Thresholds for delay
measurement points
Value
full drive mode
50
(20% / 80%) VDDX
Unit
—
pF
V
A.7.1 Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
2
1
12
4
4
12
5
6
MSB IN²
BIT 6 . . . 1
MOSI
(OUTPUT)
10
MSB OUT²
9
BIT 6 . . . 1
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
13
3
13
LSB IN
11
LSB OUT
Figure A-6 SPI Master Timing (CPHA=0)
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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