MC68HC908QB8 Datasheet, PDF (91/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

10.4 LVI Interrupts
The LVI module does not generate interrupt requests.
LVI Interrupts
10.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.5.2 Stop Mode
If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate
a reset and bring the MCU out of stop mode.
10.6 Registers
The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset
is disabled.
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_TRIPF trip voltage and is cleared
when V_DD voltage rises above V_TRIPR. (See Table 10-1).
Table 10-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
MC68HC908QB8 Data Sheet, Rev. 1
Freescale Semiconductor
91