MC68HC908QB8 Datasheet, PDF(200/236 Page) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

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MC68HC908QB8 Datasheet, PDF (200/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

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Table 17-1. Monitor Mode Signal Requirements and Options

Mode

Serial

Communi-

IRQ RST Reset cation

(PTA2) (PTA3) Vector

Mode

Selection

PTA0 PTA1 PTA4

COP

Communication

Speed

External Bus

Baud

Clock Frequency Rate

Comments

Normal

Monitor

VTST

VDD

X

1

1

0

Disabled

9.8304

MHz

2.4576

MHz

9600

Provide external

clock at OSC1.

Forced VDD

X

$FFFF

(blank)

1

Monitor

VSS

X

$FFFF

(blank)

1

X

X

Disabled

9.8304

MHz

2.4576

MHz

9600

Provide external

clock at OSC1.

X

X Disabled X

3.2 MHz

(Trimmed)

9600

Internal clock is

active.

User

X

X

Not

$FFFF

X

X

X Enabled

X

X

X

MON08

Function

[Pin No.]

VTST

[6]

RST

[4]

â

COM MOD0 MOD1

[8]

[12] [10]

â

OSC1

[13]

â

â

1. PTA0 must have a pullup resistor to VDD in monitor mode.

2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus

frequency / 256 and baud rate using internal oscillator is bus frequency / 335.

3. External clock is a 9.8304 MHz oscillator on OSC1.

4. Lowering VTST once monitor mode is entered allows the clock source to be controlled by the OSCSC register.

5. X = donât care

6. MON08 pin refers to P&E Microcomputer Systemsâ MON08-Cyclone 2 by 8-pin connector.

NC 1

NC 3

NC 5

NC 7

NC 9

NC 11

OSC1 13

VDD 15

2 GND

4 RST

6 IRQ

8 PTA0

10 PTA4

12 PTA1

14 NC

16 NC

17.3.1.1 Normal Monitor Mode

RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is

applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in

monitor mode, but the pin functions will be determined by the settings in the configuration registers (see

Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and

BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.

If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to

IRQ.

MC68HC908QB8 Data Sheet, Rev. 1

200

Freescale Semiconductor

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