MC68HC908QB8 Datasheet, PDF (26/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

Memory
Addr.
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
Register Name
ESCI Status Register 2
(SCS2)
See page 129.
ESCI Data Register
(SCDR)
See page 129.
ESCI Baud Rate Register
(SCBR)
See page 130.
ESCI Prescaler Register
(SCPSC)
See page 131.
ESCI Arbiter Control
Register (SCIACTL)
See page 135.
ESCI Arbiter Data Register
(SCIADAT)
See page 136.
Keyboard Status and
Control Register (KBSCR)
See page 87.
Keyboard Interrupt
Enable Register (KBIER)
See page 88.
Keyboard Interrupt Polarity
Register (KBIPR)
See page 88.
IRQ Status and Control
Register (INTSCR)
See page 81.
Configuration Register 2
(CONFIG2)⁽¹⁾
See page 57.
Bit 7
6
5
4
3
Read: 0
0
0
0
0
Write:
Reset: 0
0
0
0
0
Read: R7
R6
R5
R4
R3
Write: T7
T6
T5
T4
T3
Reset:
Unaffected by reset
Read:
Write:
LINT
LINR
SCP1
SCP0
R
Reset: 0
0
0
0
0
Read:
Write:
PDS2
PDS1
PDS0 PSSB4 PSSB3
Reset: 0
0
0
0
0
Read:
Write:
AM1
ALOST
AM0
ACLK
AFIN
Reset: 0
0
0
0
0
Read: ARD7
ARD6
ARD5
ARD4
ARD3
Write:
Reset: 0
0
0
0
0
Read: 0
0
0
0
KEYF
Write:
Reset: 0
0
0
0
0
Read: 0
Write:
AWUIE KBIE5 KBIE4 KBIE3
Reset: 0
0
0
0
0
Read: 0
Write:
0
KBIP5 KBIP4 KBIP3
Reset: 0
0
0
0
0
Read: 0
0
0
0
IRQF
Write:
Reset: 0
0
0
0
0
Read:
Write:
IRQPUD
IRQEN
R
R
R
Reset: 0
0
0
0
0
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
2
1
0
BKF
0
0
R2
R1
T2
T1
SCR2
0
PSSB2
0
ARUN
SCR1
0
PSSB1
0
AROVFL
0
ARD2
0
ARD1
0
0
ACKK
0
0
IMASKK
0
KBIE2 KBIE1
0
0
KBIP2 KBIP1
0
0
0
ACK
IMASK
0
0
ESCIBDSRC
OSCENIN-
STOP
0
0
Bit 0
RPF
0
R0
T0
SCR0
0
PSSB0
0
ARD8
0
ARD0
0
MODEK
0
KBIE0
0
KBIP0
0
MODE
0
RSTEN
0⁽²⁾
$001F
Configuration Register 1
(CONFIG1)⁽¹⁾
See page 58.
Read:
Write: ^COPRS
Reset: 0
LVISTOP LVIRSTD LVIPWRD LVITRIP
0
0
0
0⁽²⁾
1. One-time writable register after each reset.
2. LVITRIP reset to 0 by a power-on reset (POR) only.
SSREC
0
STOP
0
COPD
0
TIM Status and Control ^{Read: TOF}
TOIE TSTOP
0
0
$0020
Register (TSC) Write: 0
TRST
PS2
PS1
PS0
See page 183. Reset: 0
0
1
0
0
0
0
0
TIM Counter Register High ^{Read: Bit 15}
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$0021
(TCNTH) Write:
See page 185. _{Reset: 0}
0
0
0
0
0
0
0
= Unimplemented
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68HC908QB8 Data Sheet, Rev. 1
26
Freescale Semiconductor