MC68HC908QB8 Datasheet, PDF (55/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

Registers
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 9.8.2 Keyboard Interrupt Enable
Register (KBIER).
4.6.4 Configuration Register 2
The configuration register 2 (CONFIG2), is used to allow the bus clock source to run in STOP. In this case,
the clock, BUSCLKX4 will be used to drive the AWU request generator.
Read:
Write:
Reset:
Bit 7
IRQPUD
0
6
5
4
3
2
1
IRQEN
R
R
R ESCI-BDSRC OSCENINSTOP
0
0
0
0
0
0
Figure 4-5. Configuration Register 2 (CONFIG2)
Bit 0
RSTEN
0
OSCENINSTOP — Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the bus clock source (BUSCLKX4) to generate clocks for the
AWU in stop mode. See 11.8.1 Oscillator Status and Control Register for information on enabling the
external clock sources.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
NOTE
IRQPUD, IRQEN, ESCIBDSRC, and RSTEN bits are not used in conjuction
with the auto wakeup feature. To see a description of these bits, see
Chapter 5 Configuration Register (CONFIG).
4.6.5 Configuration Register 1
The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be
based on the COPRS bit along with the clock source for the AWU.
Bit 7
6
Read:
COPRS LVISTOP
Write:
Reset: POR:
0
0
0
0
U = Unaffected
5
4
LVIRSTD LVIPWRD
0
0
0
0
3
LVITRIP
U
0
2
SSREC
0
0
1
STOP
0
0
Figure 4-6. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
0
MC68HC908QB8 Data Sheet, Rev. 1
Freescale Semiconductor
55