MC68HC908QB8 Datasheet, PDF (41/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

Functional Description
When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1.
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode
8-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f_Bus ≥ f_ADCK)
8-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f_Bus ≥ f_ADCK)
10-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f_Bus ≥ f_ADCK)
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
Subsequent continuous (f_Bus ≥ f_ADCK)
ACLKEN
0
1
X
0
1
X
0
1
X
0
1
X
Maximum Conversion Time
18 ADCK + 3 bus clock
18 ADCK + 3 bus clock + 5 µs
16 ADCK
38 ADCK + 3 bus clock
38 ADCK + 3 bus clock + 5 µs
36 ADCK
21 ADCK + 3 bus clock
21 ADCK + 3 bus clock + 5 µs
19 ADCK
41 ADCK + 3 bus clock
41 ADCK + 3 bus clock + 5 µs
39 ADCK
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits.
For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input
clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single
10-bit conversion is:
21 ADCK cycles
3 bus cycles
Maximum Conversion time = _{16 MHz/8}
+
4 MHz
= 11.25 µs
Number of bus cycles = 11.25 µs x 4 MHz = 45 cycles
NOTE
The ADCK frequency must be between f_ADCK minimum and f_ADCK
maximum to meet A/D specifications.
MC68HC908QB8 Data Sheet, Rev. 1
Freescale Semiconductor
41