MC68HC908QB8 Datasheet, PDF (172/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

Serial Peripheral Interface (SPI) Module
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register.
1 = SPTE interrupt requests enabled
0 = SPTE interrupt requests disabled
15.8.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Read:
Write:
Reset:
Bit 7
SPRF
6
ERRIE
5
OVRF
4
MODF
3
SPTE
2
MODFEN
1
SPR1
0
0
0
0
1
0
0
= Unimplemented
Figure 15-14. SPI Status and Control Register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF interrupt, user software can clear SPRF by reading the SPI status and control register
with SPRF set followed by a read of the SPI data register.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate interrupt requests.
1 = MODF and OVRF can generate interrupt requests
0 = MODF and OVRF cannot generate interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register.
1 = Overflow
0 = No overflow
MC68HC908QB8 Data Sheet, Rev. 1
172
Freescale Semiconductor