MC68HC908QB8 Datasheet, PDF (140/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
V_DD
INTERNAL
PULL-UP
÷2
CLOCK
CONTROL
CLOCK GENERATORS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
FORCED MON MODE ENTRY (FROM MENRST MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 14-1. SIM Block Diagram
14.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 14-2.
FROM
OSCILLATOR
FROM
OSCILLATOR
BUSCLKX4
BUSCLKX2
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 14-2. SIM Clock Signals
MC68HC908QB8 Data Sheet, Rev. 1
140
Freescale Semiconductor