MC68HC908QB8 Datasheet, PDF (152/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

System Integration Module (SIM)
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 14-17 shows stop mode entry timing and
Figure 14-18 shows the stop mode recovery time from interrupt or break
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
ADDRESS BUS
STOP ADDR
STOP ADDR + 1
SAME
SAME
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 14-17. Stop Mode Entry Timing
BUSCLKX4
STOP RECOVERY PERIOD
INTERRUPT
ADDRESS BUS
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
Figure 14-18. Stop Mode Recovery from Interrupt
SP – 2
SP – 3
14.8 SIM Registers
The SIM has two memory mapped registers.
14.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
Write:
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 14-19. SIM Reset Status Register (SRSR)
MC68HC908QB8 Data Sheet, Rev. 1
152
Freescale Semiconductor