MC68HC908QB8 Datasheet, PDF (162/236 Pages) Freescale Semiconductor, Inc – To provide the most up-to-date information, the revision of our documents

Serial Peripheral Interface (SPI) Module
BUS
CLOCK
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
WRITE
TO SPDR
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
LATEST
SPSCK = BUS CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = BUS CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = BUS CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SPSCK = BUS CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 15-7. Transmission Start Delay (Master)
MC68HC908QB8 Data Sheet, Rev. 1
162
Freescale Semiconductor