S9S12G64F0CLF Datasheet, PDF (755/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Timer Module (TIM16B8CV3)
Register
Name
0x0021
PAFLG
0x0022
PACNTH
0x0023
PACNTL
0x0024–0x002B
Reserved
0x002C
OCPD
0x002D
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
R
0
W
R
PACNT15
W
R
PACNT7
W
R
W
R
OCPD7
W
R
0
PACNT14
PACNT6
OCPD6
0
PACNT13
PACNT5
OCPD5
0
PACNT12
PACNT4
OCPD4
0
PACNT11
PACNT3
OCPD3
0
PACNT10
PACNT2
OCPD2
PAOVF
PACNT9
PACNT1
OCPD1
PAIF
PACNT8
PACNT0
OCPD0
0x002E
PTPSR
0x002F
Reserved
R
PTPS7
W
R
W
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
Figure 23-5. TIM16B8CV3 Register Summary (Sheet 2 of 2)
1 _{The register is available only if corresponding channel exists.}
PTPS1
PTPS0
23.3.2.1 Timer Input Capture/Output Compare Select (TIOS)
Module Base + 0x0000
R
W
Reset
7
IOS7
0
6
IOS6
5
IOS5
4
IOS4
3
IOS3
2
IOS2
1
IOS1
0
0
0
0
0
0
Figure 23-6. Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
Table 23-2. TIOS Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
7:0
IOS[7:0]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding implemented channel acts as an input capture.
1 The corresponding implemented channel acts as an output compare.
0
IOS0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
757