S9S12G64F0CLF Datasheet, PDF (348/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
Figure 8-32. Scenario 4a
SCR1=0100 _State1
M0
State2 ^SCR2=0011
M1
M2
M0
M1
SCR3=0001 ^{State 3}
Final State
M1
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
Figure 8-33. Scenario 4b (with 2 comparators)
SCR1=0110 _State1
M0
State2 ^SCR2=1100
M2
SCR3=1110 ^{State 3}
M0
M2
M2
M01
Final State
M1 disabled in
range mode
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
This however violates the S12SDBGV1 specification, which states that a match leading to final state
always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel
number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on
simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state
then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG
would break on a simultaneous M0/M2.
MC9S12G Family Reference Manual, Rev.1.23
350
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