S9S12G64F0CLF Datasheet, PDF (739/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Timer Module (TIM16B6CV3)
Table 22-7. Compare Result Output Action
OMx
OLx
0
0
0
1
1
0
1
1
Action
No output compare
action on the timer output signal
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
22.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Module Base + 0x000A
7
6
5
4
R
RESERVED RESERVED RESERVED RESERVED
W
3
EDG5B
2
EDG5A
Reset
0
0
0
0
0
0
Figure 22-12. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
Module Base + 0x000B
R
W
Reset
7
EDG3B
0
Read: Anytime
Write: Anytime.
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
0
0
0
0
0
Figure 22-13. Timer Control Register 4 (TCTL4)
1
EDG0B
0
0
EDG0A
0
Table 22-8. TCTL3/TCTL4 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
5:0
EDGnB
EDGnA
Description
Input Capture Edge Control — These six pairs of control bits configure the input capture edge detector circuits.
Table 22-9. Edge Detector Circuit Configuration
EDGnB
0
0
1
EDGnA
0
1
0
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
741