S9S12G64F0CLF Datasheet, PDF (227/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Field
7-0
PTP
Table 2-61. PTP Register Field Descriptions
Description
Port P general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
2.4.3.35 Port P Input Register (PTIP)
Address 0x0259 (G1, G2)
7
R PTIP7
W
Reset
0
Address 0x0259 (G3)
6
PTIP6
0
7
6
R
0
0
W
Reset
0
0
1 _{Read: Anytime}
Write:Never
5
PTIP5
0
4
PTIP4
0
3
PTIP3
0
2
PTIP2
0
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
0
0
0
0
Figure 2-36. Port P Input Register (PTIP)
Access: User read only¹
1
PTIP1
0
PTIP0
0
0
Access: User read only¹
1
PTIP1
0
PTIP0
0
0
Field
7-0
PTIP
Table 2-62. PTIP Register Field Descriptions
Description
Port P input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
229