S9S12G64F0CLF Datasheet, PDF (222/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.28 Port M Input Register (PTIM)
Address 0x0251 (G1, G2)
7
6
R
0
0
W
Reset
0
0
Address 0x0251 (G3)
7
6
R
0
0
W
Reset
0
0
1 _{Read: Anytime}
Write:Never
5
4
3
2
0
0
PTIM3
PTIM2
0
0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
Figure 2-29. Port M Input Register (PTIM)
Access: User read only¹
1
PTIM1
0
PTIM0
0
0
Access: User read only¹
1
PTIM1
0
PTIM0
0
0
Field
3-0
PTIM
Table 2-53. PTIM Register Field Descriptions
Description
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.29 Port M Data Direction Register (DDRM)
Address 0x0252 (G1, G2)
7
R
0
W
Reset
0
Address 0x0252 (G3)
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
DDRM3
DDRM2
0
0
0
0
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-30. Port M Data Direction Register (DDRM)
Access: User read/write¹
1
0
DDRM1
DDRM0
0
0
Access: User read/write¹
1
0
DDRM1
DDRM0
0
0
MC9S12G Family Reference Manual, Rev.1.23
224
Freescale Semiconductor