S9S12G64F0CLF Datasheet, PDF (746/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Timer Module (TIM16B6CV3)
PTPSR[7:0]
PRE-PRESCALER
PACLK
PACLK/256
PACLK/65536
CLK[1:0]
MUX
PR[2:1:0]
PRESCALER
1
MUX
0
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CHANNEL 0
16-BIT COMPARATOR
TC0
EDG0A EDG0B
CHANNEL 1
16-BIT COMPARATOR
TC1
EDG1A EDG1B
CHANNEL2
CxI
CxF
TOF
INTERRUPT
TE
TOI
LOGIC
TOF
C0F
EDGE
DETECT
OM:OL0
TOV0
C0F
IOC0
CH. 0 CAPTURE
IOC0 PIN
LOGIC _{CH. 0COMPARE}
IOC0 PIN
C1F
EDGE
DETECT
OM:OL1
TOV1
C1F
IOC1
CH. 1 CAPTURE
IOC1 PIN
LOGIC _{CH. 1 COMPARE}
IOC1 PIN
CHANNELn-1
16-BIT COMPARATOR
TCn-1
EDG7A
EDG7B
Cn-1F
EDGE
DETECT
OM:OL7
TOV7
Cn-1F
IOCn-1
CH.n-1 CAPTURE
IOCn-1 PIN ^{PA INPUT}
LOGIC
IOCn-1 PIN
CH. n-1COMPARE
n is channels number.
Figure 22-22. Detailed Timer Block Diagram
22.4.1 Prescaler
The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
MC9S12G Family Reference Manual, Rev.1.23
748
Freescale Semiconductor