S9S12G64F0CLF Datasheet, PDF (246/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.64 Port AD Interrupt Flag Register (PIF1AD)
Address 0x027F
R
W
Reset
7
PIF1AD7
0
1 _{Read: Anytime}
Write: Anytime
6
PIF1AD6
5
PIF1AD5
4
PIF1AD4
3
PIF1AD3
2
PIF1AD2
0
0
0
0
0
Figure 2-63. Port AD Interrupt Flag Register (PIF1AD)
Access: User read/write¹
1
0
PIF1AD1 PIF1AD0
0
0
Table 2-90. PIF1AD Register Field Descriptions
Field
Description
7-0
PIF1AD
Port AD interrupt flag—
This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and
Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
MC9S12G Family Reference Manual, Rev.1.23
248
Freescale Semiconductor