S9S12G64F0CLF Datasheet, PDF (1109/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Data Sheet

192 KByte Flash Module (S12FTMRG192K2V1)
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 30-20. Flash Reserved3 Register (FRSV3)
All bits in the FRSV3 register read 0 and are not writable.
30.3.2.15 Flash Reserved4 Register (FRSV4)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 30-21. Flash Reserved4 Register (FRSV4)
All bits in the FRSV4 register read 0 and are not writable.
30.3.2.16 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
3
2
1
0
R
NV[7:0]
W
Reset
F¹
F¹
F¹
F¹
F¹
F¹
F¹
F¹
= Unimplemented or Reserved
Figure 30-22. Flash Option Register (FOPT)
1 _{Loaded from IFR Flash configuration field, during reset sequence.}
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 30-4) as indicated
by reset condition F in Figure 30-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Freescale Semiconductor
MC9S12G Family Reference Manual, Rev.1.23
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