MC68HC908JG16 Datasheet, PDF (71/324 Pages) Motorola, Inc – Microcontrollers

Configuration Register (CONFIG)
Configuration Register
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 2048
OSCDCLK cycles instead of a 4096 OSCDCLK cycle delay.
1 = Stop mode recovery after 2048 OSCDCLK cycles
0 = Stop mode recovery after 4096 OSCDCLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 17. Computer Operating Properly (COP).)
1 = COP timeout period is 2¹³ – 2⁴ OSCDCLK cycles
0 = COP timeout period is 2¹⁸ – 2⁴ OSCDCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 17. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor
Configuration Register (CONFIG)
Technical Data
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