MC68HC908JG16 Datasheet, PDF (116/324 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-18 shows stop mode entry timing.
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction
Figure 8-18. Stop Mode Entry Timing
OSCDCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-19. Stop Mode Recovery from Interrupt or Break
Technical Data
116
System Integration Module (SIM)
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor