MC68HC908JG16 Datasheet, PDF (262/324 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Ports
DDRB0 — Data Direction Register B Bit
This read/write bit control PTB0 data direction. Reset clears DDRB0,
configuring PTB0 pin as input.
1 = PTB0 pin configured as output
0 = PTB0 pin configured as input
NOTE: Avoid glitches on PTB0 pin by writing to the port B data register before
changing data direction register B bit from 0 to 1.
Figure 14-7 shows the port B I/O circuit logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRB0
PTB0
PTB0
READ PTB ($0001)
Technical Data
262
Figure 14-7. Port B I/O Circuit
When bit DDRB0 is a logic 1, reading address $0001 reads the PTB0
data latch. When bit DDRB0 is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 14-3 summarizes
the operation of the PTB0 pin.
Table 14-3. Port B Pin Functions
DDRB0
Bit
PTB0 Bit
I/O Pin Mode
Accesses
to DDRB
Read/Write
0
X⁽¹⁾
Input, Hi-Z⁽²⁾
DDRB0
1
X
Output
DDRB0
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTB
Read
Pin
PTB0
Write
PTB0⁽³⁾
PTB0
Input/Output (I/O) Ports
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor