 English |
|
|
|
|
|
|
|
| MC68HC908JG16 Datasheet, PDF (298/324 Pages) Motorola, Inc – Microcontrollers | |||
| |||
| ◁ |
Low-Voltage Inhibit (LVI)
VDD
LVID
LOW VDD
DETECTOR
VDD > VLVR = 0
VDD < VLVR = 1
LVI5OR3
VREG
LVIDR
LVI RESET
LOW VREG
DETECTOR
VDD > VLVRR = 0
VDD < VLVRR = 1
Figure 18-1. LVI Module Block Diagram
18.4 Functional Description
Figure 18-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains independent bandgap reference
circuit and comparator for monitoring the VDD voltage and the VREG
voltage. An LVI reset performs a MCU internal reset and drives the RST
pin low to provide low-voltage protection to external peripheral devices.
18.4.1 Low VDD Detector
The low VDD detector circuit monitors the VDD voltage and forces a LVI
reset when the VDD voltage falls below the trip voltage. The LVI5OR3 bit
in the configuration register (CONFIG) selects the trip point voltage. The
VDD LVI circuit can be disabled by the setting the LVID bit in CONFIG.
See 8.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of the
interaction between the SIM and the LVI.
Technical Data
298
Low-Voltage Inhibit (LVI)
MC68HC908JG16 â Rev. 1.1
Freescale Semiconductor
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese