MC68HC908JG16 Datasheet, PDF (218/324 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface
12.5.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 12-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
RxD
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
Figure 12-6. Receiver Data Sampling
Technical Data
218
Serial Communications Interface Module (SCI)
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor