MC68HC908JG16 Datasheet, PDF (248/324 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
13.4.1 ADC Port I/O Pins
PTA7–PTA0 are general-purpose I/O pins that are shared with the ADC
channels. The channel select bits, ADCH[4:0], in the ADC status and
control register define which ADC channel/port pin will be used as the
input signal. The ADC overrides the port I/O logic by forcing that pin as
input to the ADC. The remaining ADC channels/port pins are controlled
by the port I/O logic and can be used as general-purpose I/O. Writes to
the port register or DDR will not have any affect on the port pin that is
selected by the ADC. Read of a port pin which is in use by the ADC will
return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit
is at logic 1, the value in the port data latch is read.
13.4.2 Voltage Conversion
NOTE:
When the input voltage to the ADC equals to V_REFH, the ADC converts
the signal to $FF (full scale). If the input voltage equals to V_REFL, the
ADC converts it to $00. Input voltages between V_REFH and V_REFL is a
straight-line linear conversion. All other input voltages will result in $FF
if greater than V_REFH and $00 if less than V_REFL.
Input voltage should not exceed the analog supply voltages.
13.4.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles, therefore:
Conversion time = ^{16 to17 ADC cycles}
ADC frequency
Number of bus cycles = conversion time × bus frequency
For example: with a 6MHz bus clock and divide-by-4 prescaler, the ADC
clock is 1.5MHz, then one conversion will take 10.67µs to complete.
NOTE:
The ADC frequency must be between t_ADIC minimum and t_ADIC
maximum to meet ADC specifications. (See 20.13 ADC Electrical
Characteristics.)
Technical Data
248
Analog-to-Digital Converter (ADC)
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor