MC68HC908JG16 Datasheet, PDF (253/324 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
13.8.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address: $0062
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 13-4. ADC Data Register (ADR)
13.8.3 ADC Input Clock Register
The ADC input clock register (ADICLK) selects the clock frequency for
the ADC.
Address: $0063
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-5. ADC Input Clock Register (ADICLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divider used by the ADC
to generate the internal ADC clock. Table 13-2 shows the available
clock configurations. The ADC clock should be set to approximately
1.5 MHz.
NOTE:
The ADC frequency must be between t_ADIC minimum and t_ADIC
maximum to meet ADC specifications. (See 20.13 ADC Electrical
Characteristics.)
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Technical Data
253