MC68HC908JG16 Datasheet, PDF (251/324 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
13.8 I/O Registers
Three I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC input clock register (ADICLK)
13.8.1 ADC Status and Control Register
Function of the ADC status and control register is described here.
Address:
Read:
Write:
Reset:
$0061
Bit 7
COCO
0
6
5
AIEN ADCO
0
0
= Unimplemented
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Figure 13-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written, or whenever the ADC
data register is read. Reset clears this bit.
If the AIEN bit is a logic 1, the COCO becomes a read/write bit, which
should be cleared to logic 0 for CPU to service the ADC interrupt
request. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status and control register is written. Reset clears the
AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Technical Data
251