MC68HC908JG16 Datasheet, PDF (119/324 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Registers
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
USB — Universal Serial Bus Reset Bit
1 = Last reset caused by the USB module
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
8.8.3 SIM Break Flag Control Register (SBFCR)
The SIM break flag control register contains a bit that enables software
to clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R = Reserved
Figure 8-22. SIM Break Flag Control Register (SBFCR)
MC68HC908JG16 — Rev. 1.1
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
119