K60P144M100SF2V2 Datasheet, PDF (68/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
Table 50. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid^{1 —}
25
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S11
S12
S15
S13
S19
S15
S12
S15
S16
S17
S18
S16
S14
S16
Figure 30. I2S/SAI timing — slave modes
6.8.11.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 51. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
S1
S2
S3
S4
S5
S6
Characteristic
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
Min.
1.71
62.5
45%
250
45%
—
0
Max.
3.6
—
55%
—
55%
45
—
Unit
V
ns
MCLK period
ns
BCLK period
ns
ns
Table continues on the next page...
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
68
Preliminary
Freescale Semiconductor, Inc.
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