K60P144M100SF2V2 Datasheet, PDF (29/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol
J_{cyc_fll}
t_{fll_acquire}
f_vco
I_pll
I_pll
f_{pll_ref}
J_{cyc_pll}
Description
Min.
FLL period jitter
—
• f_VCO = 48 MHz
• f_VCO = 98 MHz
—
FLL target frequency acquisition time
—
PLL
VCO operating frequency
48.0
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 48)
PLL operating current
• PLL @ 48 MHz (f_{osc_hi_1} = 8 MHz, f_{pll_ref} =
—
2 MHz, VDIV multiplier = 24)
PLL reference frequency range
2.0
PLL period jitter (RMS)
• f_vco = 48 MHz
—
• f_vco = 100 MHz
—
Typ.
180
150
—
—
1060
600
—
120
50
Max.
—
—
1
100
—
—
4.0
—
—
Unit
Notes
ps
ms
6
MHz
µA
7
µA
7
MHz
8
ps
ps
J_{acc_pll}
PLL accumulated jitter over 1µs (RMS)
• f_vco = 48 MHz
• f_vco = 100 MHz
8
—
1350
—
ps
—
600
—
ps
D_lock
D_unl
t_{pll_lock}
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
± 1.49
—
± 2.98
%
± 4.47
—
± 5.97
%
—
—
150 × 10^-6
s
9
+ 1075(1/
f_{pll_ref})
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δf_{dco_t}) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
29
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