K60P144M100SF2V2 Datasheet, PDF (66/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
Table 48. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid —
15
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid^{1 —}
25
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
S11
S12
S15
S13
S19
S15
S12
S15
S16
S17
S18
S16
S14
S16
Figure 28. I2S/SAI timing — slave modes
6.8.11.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 49. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
S1
S2
S3
Characteristic
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
Min.
1.71
40
45%
80
Max.
3.6
—
55%
—
Unit
V
ns
MCLK period
ns
Table continues on the next page...
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
66
Preliminary
Freescale Semiconductor, Inc.
General Business Information