K60P144M100SF2V2 Datasheet, PDF (38/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
FB1
FB2
FB3
FB4
FB5
Description
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Min.
2.7
—
20
—
0.5
8.5
0.5
Max.
3.6
FB_CLK
—
11.5
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
Notes
1
1
2
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
38
Preliminary
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