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K60P144M100SF2V2 Datasheet, PDF (16/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family
General
Table 5. Power mode transition operating behaviors
Symbol Description
Min.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
—
300
μs
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS1 → RUN
—
112
μs
• VLLS2 → RUN
—
74
μs
• VLLS3 → RUN
—
73
μs
• LLS → RUN
—
5.9
μs
• VLPS → RUN
—
5.8
μs
• STOP → RUN
—
4.2
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
Notes
1
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
Min.
—
—
—
Typ.
Max.
Unit
—
See note
mA
32
TBD
mA
34
TBD
mA
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
46
TBD
mA
—
48
TBD
mA
—
TBD
TBD
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
—
20
—
mA
peripheral clocks disabled
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
—
9
—
mA
all peripheral clocks disabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
—
1.12
—
mA
peripheral clocks disabled
IDD_VLPR Very-low-power run mode current at 3.0 V — all
—
1.71
—
mA
peripheral clocks enabled
Table continues on the next page...
Notes
1
2
3, 4
2
5
6
7
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
16
Preliminary
Freescale Semiconductor, Inc.
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