K60P144M100SF2V2 Datasheet, PDF (48/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol Description
G
Gain⁴
Conditions
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
Min.
Typ.¹
Max.
Unit
Notes
0.95
1
1.05
1.9
2
2.1
R_AS < 100Ω
3.8
4
4.2
7.6
8
8.4
15.2
16
16.6
30.0
31.6
33.2
58.8
63.3
67.8
BW
PSRR
Input signal
bandwidth
Power supply
rejection ratio
• 16-bit modes
• < 16-bit modes
Gain=1
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
V_OFS
T_GSW
dG/dT
Input offset
voltage
Gain switching
settling time
Gain drift over full
temperature range
• Gain=1
• Gain=64
dG/dV_DDA Gain drift over
supply voltage
• Gain=1
• Gain=64
E_IL
Input leakage
error
All modes
—
—
4
—
—
40
—
-84
—
—
-84
—
—
-85
—
—
0.2
—
—
—
10
—
6
10
—
31
42
—
0.07
0.21
—
0.14
0.31
I_In × R_AS
V_PP,DIFF
Maximum
differential input
signal swing
SNR
Signal-to-noise
ratio
• Gain=1
• Gain=64
where V_X = V_REFPGA × 0.583
80
90
—
52
66
—
Table continues on the next page...
kHz
kHz
dB
V_DDA= 3V
±100mV,
f_VDDA= 50Hz,
60Hz
dB
V_CM=
dB
500mVpp,
f_VCM= 50Hz,
100Hz
mV Output offset =
V_OFS*(Gain+1)
µs
5
ppm/°C
ppm/°C
%/V
%/V
mV
V
V_DDA from 1.71
to 3.6V
I_In = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
6
dB
16-bit
dB
differential
mode,
Average=32
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
48
Preliminary
Freescale Semiconductor, Inc.
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