K60P144M100SF2V2 Datasheet, PDF (57/80 Pages) Freescale Semiconductor, Inc – K60 Sub-Family

Peripheral operating requirements and behaviors
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 38. MII signal switching specifications
Symbol
—
MII1
Description
RXCLK frequency
RXCLK pulse width high
MII2
RXCLK pulse width low
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
—
TXCLK frequency
MII5
TXCLK pulse width high
MII6
TXCLK pulse width low
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
Min.
—
35%
35%
5
5
—
35%
35%
2
—
Max.
25
65%
65%
—
—
25
65%
65%
—
25
Unit
MHz
RXCLK
period
RXCLK
period
ns
ns
MHz
TXCLK
period
TXCLK
period
ns
ns
TXCLK (input)
TXD[n:0]
TXEN
TXER
MII6
MII5
MII8
MII7
Valid data
Valid data
Valid data
Figure 20. MII transmit signal timing diagram
K60 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
57
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