MC68HC05P4A Datasheet, PDF (65/72 Pages) Advanced Analogic Technologies – Microcontrollers

IRQ (PIN)
IRQ₁
•
•
•
IRQ_n
RQ (MCU)
t _ILIH
t _ILIL
t _ILIH
3.3-Volt Control Timing
Edge-Sensitive Trigger Condition
The minimum pulse width (t_ILIH) is either
125 ns (V_DD = 5 V) or 250 ns (V_DD = 3 V).
The period t_ILIL should not be less than
the number of t_cyc cycles it takes to
execute the interrupt service routine
plus 19 t_cyc cycles.
Level-Sensitive Trigger Condition
If after servicing an interrupt the IRQ
remains low, then the next interrupt is
recognized.
NORMALLY
USED WITH
WIRE-ORed
CONNECTION
Figure 12-3. External Interrupt Timing
t _VDDR
VDD
VDD THRESHOLD (TYPICALLY 1-2 V)
S C1 PIN
4064 t_cyc
INTE RNAL
CLOCK
INTE RNAL
A DDRES S
BUS
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
INTE RNAL
DATA
NEW
BUS
PCH
Notes:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. An internal POR reset is triggered as V_DD rises through a threshold (typically 1–2 V).
Figure 12-4. Power-On Reset Timing
1FFF
NEW
PCL
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
65