MC68HC05P4A Datasheet, PDF (32/72 Pages) Advanced Analogic Technologies – Microcontrollers

Simple Serial Input/Output Port (SIOP)
7.2.2 Serial Data Out (SDO)
A mask programmable option will be included to allow data to be transmitted in either MSB first format or
LSB first format. In either case, the state of the SDO pin always will reflect the value of the first bit received
on the previous transmission if there was one. Prior to enabling the SIOP, PB5 can be initialized to
determine the beginning state if necessary. While the SIOP is enabled, PB5 can not be used as a
standard output since that pin is coupled to the last stage of the serial shift register. On the first falling
edge of SCK, the first data bit to be shifted out is presented to the output pin.
7.2.3 Serial Data In (SDI)
The SDI pin becomes an input as soon as the SIOP is enabled. New data may be presented to the SDI
pin on the falling edge of SCK. Valid data must be present at least 100 ns before the rising edge of the
clock and remain valid for 100 ns after the edge.
SCK
SDO
SDI
BIT 1
BIT 2
BIT 3
BIT 7
BIT 1
BIT 2
BIT 3
BIT 7
Figure 7-2. Serial I/O Port Timing
BIT 8
BIT 8
7.3 SIOP Registers
The SIOP registers are described here.
7.3.1 SIOP Control Register
This register is located at address $000A and contains two bits.
Address: $000A
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
SPE
MSTR
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
SPE — Serial Peripheral Enable Bit
When set, this bit enables the serial I/O port and initializes the port B DDR such that PB5 (SDO) is
output, PB6 (SDI) is input, and PB7 (SCK) is input (slave mode only). The port B DDR can be altered
subsequently as the application requires and the port B data register (except for PB5) can be
manipulated as usual. However, these actions could affect the transmitted or received data. When
SPE is cleared, port B reverts to standard parallel I/O without affecting the port B data register or DDR.
SPE is readable and writable any time but clearing SPE while a transmission is in progress will abort
the transmission, reset the bit counter, and return port B to its normal I/O function. Reset clears this bit.
MC68HC05P4A Data Sheet, Rev. 7.1
32
Freescale Semiconductor