MC68HC05P4A Datasheet, PDF (39/72 Pages) Advanced Analogic Technologies – Microcontrollers

Timer During Wait or Halt Mode
A problem can occur when using the timer overflow function and reading the free-running counter at
random times to measure an elapsed time. Without incorporating the proper precautions into software,
the timer overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as the free-running
counter (at address $18 and $19); therefore, this alternate register can be read at any time without
affecting the timer overflow flag in the timer status register.
8.7 Timer During Wait or Halt Mode
The CPU clock halts during the wait or halt mode, but the timer remains active. If interrupts are enabled,
a timer interrupt will cause the processor to exit the wait mode.
8.8 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If
RESET is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs
at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags to wake up
the MCU, but when the MCU does wake up, there is an active input capture flag and data from the first
valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag
or data remains, even if a valid input capture edge occurred.
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
39