MC68HC05P4A Datasheet, PDF (38/72 Pages) Advanced Analogic Technologies – Microcontrollers

Timer
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will trigger free-running counter
transfer to the input capture register. Reset does not affect the IEDG bit.
1 = Positive edge
0 = Negative edge
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next successful output compare and
will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
8.6 Timer Status Register
The timer status register (TSR) is a read-only register containing three status flag bits.
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Write:
Reset: U
U
U
0
0
0
0
0
= Unimplemented
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag Bit
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($15) are accessed
OCF — Output Compare Flag Bit
1 = Flag set when output compare register contents match the free-running counter contents
0 = Flag cleared when TSR and output compare low register ($17) are accessed
TOF — Timer Overflow Flag Bit
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
MC68HC05P4A Data Sheet, Rev. 7.1
38
Freescale Semiconductor