MC68HC05P4A Datasheet, PDF (37/72 Pages) Advanced Analogic Technologies – Microcontrollers

Input Capture Register
free-running counter is updated every four internal bus clock cycles. The minimum time required to update
the output compare register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare
flag (OCF) is set or clear.
8.4 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch
the value of the free-running counter after the corresponding input capture edge detector senses a
defined transition. The level transition which triggers the counter transfer is defined by the corresponding
input edge bit (IEDG). Reset does not affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter, which is four internal bus clock
cycles.
The free-running counter contents are transferred to the input capture register on each proper signal
transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register
always contains the free-running counter value that corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer since they
occur on opposite edges of the internal bus clock.
8.5 Timer Control Register
The timer control register (TCR) is a read/write register containing five control bits. Three bits control
interrupts associated with the timer status register flags ICF, OCF, and TOF.
Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
ICIE
OCIE
TOIE
IEDG
OLVL
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
37