MC68HC05P4A Datasheet, PDF (19/72 Pages) Advanced Analogic Technologies – Microcontrollers

Addr.
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Introduction
Register Name
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
Timer Control Register
(TCR)
Timer Status Register
(TSR)
Input Capture MSB
(ICRH)
Input Capture LSB
(ICRL)
Output Compare MSB
(OCRH)
Output Compare LSB
(OCRL)
Counter MSB
(CRH)
Counter LSB
(CRL)
Dual Timer MSB (DTMH)
Counter Alternate Register
Dual Timer LSB (DTML)
Counter Alternate Register
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
ICIE
0
ICF
U
ICRH7
ICRL7
OCRH7
OCRL7
CRH7
CRL7
DTMH7
DTML7
OCIE
0
OCF
U
ICRH6
ICRL6
OCRH6
OCRL6
CRH6
CRL6
DTMH6
DTML6
TOIE
0
TOF
U
ICRH5
ICRL5
OCRH5
OCRL5
CRH5
CRL5
DTMH5
DTML5
0
0
0
0
0
0
0
ICRH4
0
ICRH3
Unaffected by reset
ICRL4
ICRL3
Unaffected by reset
OCRH4 OCRH3
Unaffected by reset
OCRL4 OCRL3
Unaffected by reset
CRH4
CRH3
Unaffected by reset
CRL4
CRL3
Unaffected by reset
DTMH4 DTMH3
Unaffected by reset
DTML4 DTML3
Unaffected by reset
0
IEDG OLVL
0
0
0
0
0
0
0
ICRH2
0
ICRH1
0
ICRH0
ICRL2 ICRL1 ICRL0
OCRH2 OCRH1 OCRH0
OCRL2 OCRL1 OCRL0
CRH2 CRH1 CRH0
CRL2 CRL1 CRL0
DTMH2 DTMH1 DTMH0
DTML2 DTML1 DTML0
Unimplemented
Unimplemented
Reserved
R
R
R
R
R
R
R
R
= Unimplemented U = Unaffected X = Indeterminate
Figure 2-2. I/O Registers for the MC68HC05P4A (Sheet 2 of 2)
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
19