MC68HC05P4A Datasheet, PDF (26/72 Pages) Advanced Analogic Technologies – Microcontrollers

Interrupts
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the port A pins
(PA0–PA7) to act as other IRQ interrupt sources. These sources are all combined into a single ORing
function to be latched by the IRQ latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the IRQ pin or a port A pin if
port A interrupts have been enabled. If edge-only sensitivity is chosen by a mask option, only the IRQ
latch output can activate a request to the CPU to generate the IRQ interrupt sequence. This makes the
IRQ interrupt sensitive to:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level
2. Falling edge on any enabled port A interrupt pin with all other enabled port A interrupt pins and the
IRQ pin at a high level
If level sensitivity is chosen, the active high state of the IRQ input can also activate an IRQ request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to:
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a high level
3. Low level on any enabled port A interrupt pin
4. Falling edge on any enabled port A interrupt pin with all enabled port A interrupt pins on the IRQ
pin at a high level
This interrupt is serviced by the interrupt service routine located at the address specified by the contents
of $1FFA and $1FFB. The IRQ latch is automatically cleared by entering the interrupt service routine.
4.5 Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0–PA7 port pins if enabled by individual mask
options. With pullup enabled, each port A pin can activate the IRQ interrupt function and the interrupt
operation will be the same as for inputs to the IRQ pin. Once enabled by mask option, each individual port
A pin can be disabled as an interrupt source if its corresponding DDR bit is configured for output mode.
NOTE
The BIH and BIL instructions apply to the output of the logic OR function of
the enabled PA0–PA7 interrupt pins and the IRQ pin. The BIH and BIL
instructions do not exclusively test the state of the IRQ pin.
If enabled, the PA0–PA7 pins will cause an IRQ interrupt only if these
individual pins are configured as inputs.
4.6 Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is executed regardless of the state
of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts which were
pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The
interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD.
MC68HC05P4A Data Sheet, Rev. 7.1
26
Freescale Semiconductor