MC68HC05P4A Datasheet, PDF (45/72 Pages) Advanced Analogic Technologies – Microcontrollers

Chapter 11
Instruction Set
11.1 Introduction
This section describes the M68HC05P4A addressing modes and instruction types.
11.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the
manner in which the CPU finds the data required to execute an instruction. The addressing modes are:
1. Inherent
2. Immediate
3. Direct
4. Extended
5. Indexed, no offset
6. Indexed, 8-bit offset
7. Indexed, 16-bit offset
8. Relative
11.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no memory address and are one byte long.
11.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no memory address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
11.2.3 Direct
Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are 3-byte
instructions that use direct addressing to access the operand and relative addressing to specify a branch
destination.
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
45