MC68HC05P4A Datasheet, PDF (41/72 Pages) Advanced Analogic Technologies – Microcontrollers

Chapter 9
Computer Operating Properly (COP)
9.1 Introduction
This device includes a watchdog computer operating properly (COP) feature as a mask option. The COP
is implemented with an 18-bit ripple counter. This provides a timeout period of 64 milliseconds at a bus
rate of 2 MHz. If the COP should time out, a system reset will occur and the device will be re-initialized in
the same fashion as a power-on reset (POR) or external reset.
9.2 Resetting the COP
Preventing a COP reset is done by writing a 0 to the COPR bit. This action will reset the counter and begin
the timeout period again. The COPR bit is bit 0 of address $1FF0. A read of address $1FF0 will access
the user-defined ROM data at that location.
9.3 COP During Wait or Halt Mode
The COP will continue to operate normally during wait or halt mode. The software should pull the device
out of wait or halt mode periodically and reset the COP by writing a logic 0 to the COPR bit to prevent a
COP reset.
9.4 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP
counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will
be reset after the 4064 cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP
counter will not be reset after the 4064-cycle delay and will have that many cycles already counted when
control is returned to the program.
NOTE
Halt mode is not intended for normal use. This feature is provided to keep
the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
41