MC68HC05P4A Datasheet, PDF (31/72 Pages) Advanced Analogic Technologies – Microcontrollers

Chapter 7
Simple Serial Input/Output Port (SIOP)
7.1 Introduction
This device includes a simple synchronous serial input/output (SIOP) port. The SIOP is a 3-wire
master/slave system including serial clock (SCK), serial data input (SDI), and serial data output (SDO). A
mask programmable option determines whether the SIOP is most significant bit (MSB) or least significant
bit (LSB) first.
RESET
RQ
D
C
8-BIT SHIFT REGISTER
SDO
SCK
SDI
MSB/LSB MASK OPTION
DATA BUS
Figure 7-1. SIOP Block Diagram
7.2 Signal Format
The SIOP signal format is described here.
7.2.1 Serial Clock (SCK)
The state of SCK between transmissions must be logic 1. The first falling edge of SCK signals the
beginning of a transmission. At this time, the first bit of received data is accepted at the SDI pin and the
first bit of transmitted data is presented at the SDO pin. Data is captured at the SDI pin on the rising edge
of SCK. Subsequent falling edges shift the data and accept or present the next bit. The transmission is
ended upon the eighth rising edge of SCK. The maximum frequency of SCK in slave mode is equal to E
(bus clock) divided by four. That is, for a 4-MHz oscillator input, E becomes 2 MHz and the maximum SCK
frequency is 0.5 MHz. There is no minimum SCK frequency.
In master mode, the format is identical except that the SCK pin is an output and the shift clock now
originates internally. The master mode transmission frequency is fixed at E/4.
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
31