MC68HC05P4A Datasheet, PDF (25/72 Pages) Advanced Analogic Technologies – Microcontrollers

Timer Interrupt
3. WAIT or HALT — The WAIT or HALT instruction causes all processor clocks to stop, but leaves
the timer clock running. This rest state of the processor can be cleared by reset, an external
interrupt (IRQ), or timer interrupt. These individual interrupts have no special wait vectors. See 6.3
WAIT Instruction.
4.3 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt when they are set and enabled. The interrupt
flags are in the timer status register (TSR), and the enable bits are in the timer control register (TCR). Any
of these interrupts will vector to the same interrupt service routine, located at the address specified by the
contents of memory locations $1FF8 and $1FF9.
4.4 External Interrupt
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the
falling edge of IRQ. If either the output from the internal edge detector flip-flops or the level on the IRQ
pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive only
mask 0ption is selected, the output of the internal edge detector flip-flop is sampled and the input level on
the IRQ pin is ignored. The interrupt service routine address is specified by the contents of memory
locations $1FFA and $1FFB. A block diagram of the IRQ function is shown in Figure 4-2.
IRQ PIN
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
TO BIH & BIL
INSTRUCTION
SENSING
V_DD
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
IRQ
LATCH
R
TO IRQ
PROCESSING
IN CPU
Figure 4-2. IRQ Function Block Diagram
NOTE
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $1FFA is read). Therefore, another
external interrupt pulse can be latched during the IRQ service routine.
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed to avoid the processor
re-entering the IRQ service routine.
MC68HC05P4A Data Sheet, Rev. 7.1
Freescale Semiconductor
25