MSC7116_08 Datasheet, PDF (59/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Revision History
7 Revision History
Table 36 provides a revision history for this data sheet.
Table 36. Document Revision History
Revision
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Date
Description
Apr 2004
May 2004
Aug. 2004
Sep. 2004
Jan. 2005
Mar. 2005
Apr. 2005
Oct. 2005
Dec. 2005
Nov. 2006
Apr. 2007
Jul. 2007
Aug 2007
Apr 2008
• Initial public release.
• Added ordering information and new package options.
• Updated clock parameter values.
• Updated DDR timing specifications.
• Updated I²C timing specifications.
• Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.
• Corrected EE0 port reference.
• Updated ball location for HDSP.
• Added signal HA3.
• Updated absolute maximum ratings, DDR DRAM capacitance specifications, clock parameters, reset
timing, and TDM timing.
• Added note for timing reference for I²C interface.
• Expanded GPIO timing information.
• Corrected pin T20 and K20 signal designation.
• Corrected signal names to GPAO15 and IRQ2.
• Expanded design guidelines in Chapter 4.
• Updated features list.
• Updated power specifications.
• Changed CLKIN frequency range.
• Added clock configuration information.
• Updated JTAG timings.
• Added recommended power supply ratings and updated equations to estimate power consumption.
• Updated core and total power consumption examples.
• Added information about the new mask set 1M88B. Affected all sections.
• Updated arrows in Host DMA Writing Timing figure.
• Updated boot overview in Section 4.4.3.
• Removed erroneous references to V_CCSYN and V_CCSYN1.
• Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
• Removed all references to obsolete mask set 1L44X and corresponding specification values.
• Added a note to clarify the definition of TCK timing 700 in new Table 31.
• Reworked reset and boot sections.
• Expanded I²C boot information and added SPI boot information.
• Removed obsolete part numbers.
• The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expanded
to five possible design scenarios/cases. These cases replace the previously recommended
power-up/power-down sequence recommendations. Section 3.2 has been clarified by adding subsection
headings.
• Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
59