MSC7116_08 Datasheet, PDF (52/60 Pages) Freescale Semiconductor, Inc – Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Hardware Design Considerations
Table 35. Boot Mode Source Selection
BM[3–0]
Boot
Port
Input Clock Clock
Frequency Divide
PLL
CKSEL
RNG
Bit
Core Clock
Frequency
Comments
HDI Boot Modes
0000
HDI16
< F_max
N/A
N/A
00
0
< F_max
Not clocked by the PLL.
Can boot as 8- or 16-bit HDI.
0101
HDI16
22.2-25 MHz
1
12
11
1
266–300 MHz Can boot as 8- or 16-bit HDI.
0010
HDI16
25-33.3 MHz
2
32
01
1
200–266 MHz
0111
HDI16
33-66 MHz
3
12
11
1
132–264 MHz
0100
HDI16
44.3-50 MHz
2
12
11
1
266–300 MHz
SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins
1000
SPI (SW)
< F_max
N/A
N/A
00
0
< F_max
The boot program automatically
1001
SPI (SW) 15.6-25 MHz
1
17
11
0
133–212.5 MHz ^{determines whether EEPROM}
1010
SPI (SW) 33-50 MHz
2
16
11
0
132–200 MHz ^{or Flash memory.}
1011
SPI (SW) 44.3-75 MHz
3
18
11
0
133–225 MHz
SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins
1100
SPI (SW)
< F_max
N/A
N/A
00
0
I²C Boot Modes
0001
I²C
< 100 MHz
N/A
N/A
00
0
< F_max
< 100 MHz
Boots through different set of
pins.
Not clocked by the PLL.
I²C is limited to a maximum bit
rate of 400 Kbps. With a clock
divider of 128, this limits the
maximum input clock frequency
to 100 MHz.
Reserved
0011
Reserved
—
—
—
—
—
—
—
0110
Reserved
—
—
—
—
—
—
—
1101
Reserved
—
—
—
—
—
—
—
1110
Reserved
—
—
—
—
—
—
—
1111
Reserved
—
—
—
—
—
—
—
Notes: 1. The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.
2. The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.
3. F_max is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.
3.4.3 Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates
slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher
speed. The MSC7116 can boot from an external host through the HDI16 or download a user program through the I²C port. The
boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35.
See the MSC711x Reference Manual for details of boot program operation.
3.4.3.1 HDI16 Boot
If the MSC7116 device boots from an external host through the HDI16, the port is configured as follows:
• Operate in Non-DMA mode.
• Operate in polled mode on the device side.
• Operate in polled mode on the external host side.
• External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
MSC7116 Data Sheet, Rev. 13
52
Freescale Semiconductor